28th October, 2006

Brief Introduction to PCI – Part I   

Posted in design, lowlevel, programming | by evilbitz |



This article is written in simple language and is intended for the common knowledge of the average computer user that should know what is happening under the “hood”, yet most advanced users can find this information interesting and it might introduce some new topics for them.

Before we will delve into the interesting part, let’s move through some basics. PCI is an acronym which stands for Peripheral Component Interconnect. It is the medium by which the CPU is talking with the rest of the devices in the computer. In the computer Jargon, it is called a bus. It is a set of lines that connects all the devices to the CPU and RAM (Random Access Memory) all together. For example, a sound card may be connected into a PCI slot on the Mother Board. When the operating system boots, it probes for PCI devices and get’s a list of all the devices which are connected in the system.

Each device owns the bus for just a period of time. Since there are several devices on the bus, a mechanism that determines which device may use the bus is needed. Fundamentally, this is called bus arbitration.

A PCI device also may have a need to communicate with its driver, which is a piece of software that runs in the operating system’s context and operates the device. Since there are a lot of operating systems, that same device may have several different versions of drivers, one for each OS. To communicate with the driver, the device holds an IRQ Line (Interrupt Request) and uses it to signal the CPU that the driver should be called and handle the event.

In this request, which is called an Interrupt, the driver may need to read some data from the device (think about a network packet that arrives to the machine). To pass the data (I/O), a PCI device may have two options, to pass the data by some I/O ports or by sharing a pre-determined memory region. The IRQ line and the addresses of the shared memory region are called the device’s resources.

When an interrupt occurs, the CPU stops the execution of the current software that is running and passes control to the driver. This is called pre-emption. So, the driver handles this event, and a function that is called the ISR (Interrupt Service Routine) is being executed. It reads and writes some data from the device and processes it. When a user’s software will ask for this data, the driver will have it ready.

Ok… let’s get back to PCI itself. PCI is actually the successor of an older bus called ISA, which was slower, and the predecessor of PCI-e (PCI Express ), which is newer and extremely faster. But yet, most of the hardware is designed for PCI and it is still the most common bus in the PC market. Don’t be mislead, even those “On-Board” devices which are so common those days are connected through the PCI bus. PCI slots are used for expansion.

The PCI bus is composed of 32 lines of electricity, each represents a bit, which is the smallest representation of data. It might be 0 or 1. Together, those 32 bits are composing a number in the range of 0 to 4,294,967,296. The PCI bus is working on a clock speed of 33MHz. That means that each line (bit) may be sampled in less than 1/33 of a second.

In the next article, I’ll introduce some new terms like DMA and BIOS.

Thanks for reading!



There are currently 10 responses to “Brief Introduction to PCI – Part I”

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  1. 1 On December 14th, 2006, Jesse said:

    According to http://en.wikipedia.org/wiki/PCI_Express ,
    PCI Express … should not to be mistaken for PCI-X.

    Thanks! keep up the good work.

    -Jesse

  2. 2 On December 14th, 2006, evilbitz said:

    Thanks Jesse!
    I edited the article according to your suggestion.

  3. 3 On December 20th, 2006, Florii said:

    Isn’t that supposed to be 1/33 of a millionth of a second? :) That’s what Mega means. What you said would be correct if you’re talking about a 33 Hz frequency.

    Otherwise a good introductory article ~ maybe you can also update it to show how you compute the theoretical peak transfer rate when you mention bus width and frequency. Cheers!

    Florii

  4. 4 On December 21st, 2006, abdul musawwir said:

    Can external harddrives be connected via PCI

  5. 5 On May 23rd, 2007, g kiran kumar said:

    Thanks,
    it gives a more clear picture about the functionality of PCI.

  6. 6 On May 24th, 2007, Richard said:

    W.R.T “On Board devices” connected via PCI bus — isn’t that less true these days with more and more complex system controllers?

  7. 7 On June 13th, 2007, evilbitz said:

    Richard, most of the controllers on the PC architecture are connected through some kind of PCI bus ;-)

    The CPU accesses the PCI bus through the south bridge, where it is connected, although you can connect any kind of bus to the south/north bridge. It is widely accepted to use PCI.

    PCIe is connected through the north bridge actually, so fast graphic cards for instance can access the system RAM faster (it is connected to the north bridge as well).

  8. 8 On July 11th, 2007, Jose said:

    Am I correct in assuming that the device itself possesses no external memory? Does it share memory with the hardrive or ram? and, if so, then what exactly does a device comprise of, if it is devoid of a processor and it’s own memory?

    I’m curious, evilbitz.

  9. 9 On July 27th, 2008, evilbitz said:

    Jose, most of the devices has their own memory. Basically the memory address space that is accessible to the CPU is divided into two. RAM and MMIO. And the North Bridge (MCH) decides where to route each access made by the CPU in a simple way… if it is in the RAM area, pass the access to the memory controller, if it’s not, pass the access to PCI.

  10. 10 On January 28th, 2009, Selvaraj said:

    good introduction!

    Formating Comment: Shall have a link from this page to the Part II.

    Thanks

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